A solid-state drive (SSD) is different from standard dynamic random access memory (DRAM) in that a host needs to be able to send control information to the SSD and receive status information that is generated by the SSD. Data communications between the host system and the SSD over a DRAM channel may be significantly complicated through the use of data scrambling and optionally error-correcting code (ECC) protection, and other data protection schemes. Most scrambling schemes performed by a host memory controller involve generating a pseudo-random (but deterministic) pattern and performing an exclusive-or (XOR) operation with the pattern and the data to be sent. The pattern value that the data is XORed with may be based on a fixed seed or some combination of a seed and the memory address of the transfer.
For a DDR form factor storage device, it is required that the storage device memory controller is able to descramble the data received over the memory bus to execute the command and store the data in the storage. Similarly, for data retrieved from the storage to be correctly sent back to the host system, the storage device memory controller will need to scramble the data so that the data can be recognized by the host system. This requires the storage device memory controller to be able to apply the same scrambling and/or ECC that was applied by the host memory controller. This means that the scrambling algorithm has to be reversible and cannot have dependency with data on the DDR channel in time.
Full reverse engineering of scrambling algorithms used by the host system is difficult. And even if the scrambling algorithms are known, the scrambling algorithms might vary from one vendor/platform to another.
What is needed is an improved XOR-based scrambler/descrambler for SSD communication protocols, and preferably one that does not require knowledge or full reverse engineering of the scrambling algorithm supplied by the host memory controller.